Semiconductor device and method of production thereof

ABSTRACT

An operating semiconductor layer is formed in such a manner that amorphous silicon layer is formed to be shaped so that it has a wide region and a narrow region and the narrow region is connected to the wide region at a position asymmetric to the wide region, and the amorphous silicon layer is crystallized by scanning a CW laser beam from the wide region toward the narrow region in a state that a polycrystalline silicon layer as a heat-retaining layer encloses the narrow region from a side face through the silicon oxide layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims priority of JapanesePatent Application Nos. 2001-262160, filed on Aug. 30, 2001, and2002-180425, filed on Jun. 20, 2002, the contents being incorporatedherein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. [Field of the Invention]

[0003] The present invention relates to a thin-film type semiconductordevice having an operating semiconductor layer and a method ofproduction thereof. In particular, it is favorable to apply to athin-film transistor in which a source/drain is formed on the operatingsemiconductor layer and a gate electrode is formed on a channel area.

[0004] 2. [Description of the Related Art]

[0005] Since a thin-film transistor (TFT) is formed into a very thinfine operating semiconductor layer, mounting on a large screen liquidcrystal display panel and the like is expected considering recent demandfor a big area.

[0006] For a TFT operating semiconductor layer, use of a polycrystallinesilicon layer has been studied because it has high carrier mobility andis thermally stable compared to an amorphous silicon layer (a-Si layer).At present, the methods shown below are used for forming method of theoperating semiconductor layer using the polycrystalline silicon layer.

[0007] (1) A method of forming the polycrystalline silicon layer byheating the a-Si layer between about 600° C. and about 1100° C. tocrystallize has been adopted. This method plans to form a crystalnucleus at an early stage of the heating process and to crystallize bygrowing this crystal nucleus.

[0008] (2) The a-Si layer is melted by adding laser energy to form thepolycrystalline silicon layer by crystallizing it when it is cooled.

[0009] (3) The polycrystalline silicon layer is formed directly by achemical vapor growth method or a physical evaporation method at atemperature of 600° C. or more.

[0010] Here, using a method of forming a thin-film semiconductor layeron a glass substrate as an example, disadvantages of the conventionalart are discussed. Since glass is used for a substrate material, thetemperature of the substrate is limited to 600° C. or less.

[0011] The crystal growth method described in (1) requires a heatprocessing temperature of 600° C., which corresponds to heat processingat a high temperature for the glass and causes deformation of the glass.In addition, stacking faults and twin crystals are contained in thegrown crystal in large quantity, which makes it impossible to expectformation of a polycrystalline silicon layer with excellentcrystallinity.

[0012] With the crystal growth method described in (3), a columnarcrystal is formed, which is insufficient in crystallinity because of itssmall crystal grain diameter, and a crystal showing a high mobility cannot be formed.

[0013] With the method using laser anneal described in (2), a laserwhich can be used without raising the temperature of the substrate islimited to an excimer laser. When the excimer laser is used, apolycrystalline silicon layer of high quality can be obtained, becausethe crystal grows through a molten phase. However, it has a disadvantagein that the energy range for obtaining a polycrystalline silicon layerof such a high quality is extremely narrow. Furthermore, when theexcimer laser is used, though only the thin-film silicon region on thesurface layer is melted getting a high temperature, the temperature ofthe glass itself is low. Accordingly, the cooling rate of the siliconmolten is high.

[0014] Therefore, growth from the molten occurs under a super coolingcondition and many crystal nuclei are formed which makes the crystalgrain diameter small. Generally, the range of the crystal grain diameteris about 300 nm to about 600 nm. When a thin-film polycrystallinesilicon layer is formed using the excimer laser, which assures the bestcrystallinity, the mobility of the thin-film transistor is about 200cm²/Vs, which is far smaller compared to the mobility of a singlecrystal silicon of 600 cm²/Vs. This is because the crystal graindiameter is small and the crystal grain boundary portion works as ascatterer with a strong carrier.

[0015] As above, there have conventionally been a serious disadvantagein that even the operating semiconductor layer is composed of thepolycrystalline silicon layer, the lowering of the mobility due to thecrystal grain boundary can not be restrained and the production of ahigh quality operating semiconductor layer can not be guaranteed.

SUMMARY OF THE INVENTION

[0016] An object of the present invention is to provide a thin-film typesemiconductor device which realizes extremely high mobility by formingan operating semiconductor layer from a thin-film semiconductor layerhaving a negligibly small effect of a crystal grain boundary, and toprovide a method for production of the semiconductor device whichenables the semiconductor device to be produced easily and securely.

[0017] The present invention provides the following embodiments to solvethe above-described disadvantages.

[0018] The present invention relates to a thin-film type semiconductordevice provided with an operating semiconductor layer on a substrate anda method for production thereof.

[0019] In the semiconductor device of the present invention, theoperating semiconductor layer is shaped so that a wide region and anarrow region are connected with each other. The wide region is in aflow pattern state with a large crystal grain, and a direction of acrystal grain boundary in the above-described flow pattern is formed notto be parallel to a longitudinal direction of the narrow region, whilethe narrow region is substantially in a single crystalline state.

[0020] The method for producing the semiconductor device of the presentinvention comprises the steps of: forming a semiconductor layer which isto be the operating semiconductor layer above the substrate; processingthe semiconductor layer to be shaped so that it has a wide region and anarrow region and the narrow region is connected to the wide region in amanner that the narrow region is positioned to be asymmetric withrespect to the wide region, and crystallizing the semiconductor layer byirradiating energy beam to the semiconductor layer along thelongitudinal direction of the narrow region from the wide region towardthe narrow region.

[0021] Another aspect of the method for producing the semiconductordevice of the present invention comprises the steps of: forming asemiconductor layer to be the operating semiconductor layer above thesubstrate; processing the semiconductor layer to be shaped so that ithas a wide region and a narrow region; and crystallizing thesemiconductor layer by irradiating energy beam to the semiconductorlayer in such a manner that a scanning plane of a beam spot is inclinedfrom a perpendicular position to a longitudinal direction of thesemiconductor layer.

[0022] From the above consideration, if an outbreak of the crystal grainboundary bringing about lowering of the mobility can be restrained, themobility is improved and performance of the semiconductor element can beimproved. For this purpose, it is satisfactory to structure theoperating semiconductor layer from a crystal grain having a largecrystal grain diameter and the ultimate figure of the operatingsemiconductor layer is a complete single crystal semiconductor.

[0023] In the semiconductor device according to the present invention,the operating semiconductor layer is structured such that the wideregion is in a crystalline state with a flow pattern having a largecrystal grain and the narrow region is substantially in a singlecrystalline state. Since there exists actually no crystal grain boundarydue to the flow pattern in the narrow region, therefore, when the narrowregion is used as a channel, a semiconductor device having a highmobility can be obtained without fail.

[0024] In a method of production of the semiconductor device accordingto the present invention, energy beam is irradiated to the semiconductorlayer, which is patterned to be shaped so that the narrow region isconnected to the wide region in a manner that the narrow region ispositioned to be asymmetric with respect to the wide region, along thelongitudinal direction of the narrow region from the wide region towardthe narrow region. At this time, the wide region is solidified along thedirection of the irradiation, and a flow pattern including crystalgrains having a large diameter controlled in growth direction is formedin the wide region. The crystal grain boundary is formed toward thenarrow region in the flow pattern. Though the shape of the crystal grainboundary formed with whole of respective flow patterns is symmetric withrespect to the direction of the irradiation, since the narrow region isformed to be asymmetric with respect to the wide region, the crystalgrain boundary collides against a wall in the narrow region near theboundary between the narrow region and the wide region and disappearswith high possibility, which restrains formation of the crystal grainboundary in the narrow region. Owing to this effect, an operatingsemiconductor layer in which the wide region is in a crystalline statehaving a flow pattern with a large crystal grain and the narrow regionis substantially in a single crystalline state is to be formed.

[0025] In another aspect of the method for producing the semiconductordevice of the present invention, energy beam is irradiated to thesemiconductor layer, which is patterned to be shaped so that the narrowregion and the wide region are connected to each other in a manner thatthe narrow region is positioned to be asymmetric with respect to thewide region, in such a manner that a scanning plane of a beam spot isinclined from a perpendicular position to a longitudinal direction ofthe semiconductor layer. At this time, the wide region is solidifiedalong the direction of the irradiation, and a flow pattern includingcrystal grains having a large diameter controlled in growth direction isformed in the wide region. The crystal grain boundary is formed towardthe narrow region in the flow pattern. Though the shape of the crystalgrain boundary formed with whole of respective flow patterns issymmetric with respect to the direction of the irradiation, since aninclination angle is given to the scanning plane of the beam, thecrystal grain boundary securely collides against a wall in the narrowregion near the boundary between the narrow region and the wide regionand disappears, which restrains formation of the crystal grain boundaryin the narrow region. Owing to this effect, an operating semiconductorlayer in which the wide region is in a crystalline state having a flowpattern with a large crystal grain and the narrow region issubstantially in a single crystalline state is to be formed.

[0026] The methods of production of the semiconductor device accordingto the present invention further comprise the steps of: forming aheat-retaining layer so as to cover only a side portion of the narrowregion selectively; and irradiating energy beam in this state. Then, theheat-retaining layer serves as a heat reservoir having a large heatcapacity to make cooling rate of a molten small and to control the heatdistribution of the semiconductor layer so that the position of nucleusformation and direction of crystal growth are controlled. In this case,crystallization proceeds by progress of the temperature lowering from acenter portion of the narrow region. However, since the side portion ofthe narrow region is selectively covered with the heat-retaining layer,it is the most difficult to lower the temperature of this side portionand effective crystallization can be realized. Therefore, thecrystalline state having a large crystal grain diameter can be realizedwith high reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1A, FIG. 1B, FIG. 1C and FIG. 1D are diagrammatic sectionalviews showing a method of forming an operating semiconductor layer inprocess order in a first forming method of an embodiment;

[0028]FIG. 2A, FIG. 2B, FIG. 2C and FIG. 2D are diagrammatic sectionalviews showing the method of forming the operating semiconductor layer inprocess order following to FIG. 1A, FIG. 1B, FIG. 1C and FIG. 1D;

[0029]FIG. 3 is a diagrammatic plan view showing a processed amorphoussilicon layer;

[0030]FIG. 4 is a diagrammatic plan view showing a state of theamorphous silicon layer on which a heat-retaining layer is formed;

[0031]FIG. 5 is a diagrammatic plan view showing a direction ofirradiation of a CW laser beam;

[0032]FIG. 6A and FIG. 6B are diagrammatic plan views showing a state ofthe crystal growth;

[0033]FIG. 7A, FIG. 7B, and FIG. 7C are diagrammatic plan views showinga state of the crystal growth together with a comparison example;

[0034]FIG. 8 is a diagrammatic plan view showing the operatingsemiconductor layer partially covered with a resist;

[0035]FIG. 9 is a diagrammatic plan view showing the patterned operatingsemiconductor layer;

[0036]FIG. 10 is an optical microscope photograph showing a crystallinestate of the completed operating semiconductor layer;

[0037]FIG. 11 is a diagrammatic plan view showing a state of theamorphous silicon layer of a modification example in the first formingmethod;

[0038]FIG. 12A, FIG. 12B, FIG. 12C and FIG. 12D are diagrammaticsectional views showing a method of forming an operating semiconductorlayer in process order in a second forming method of an embodiment;

[0039]FIG. 13A, FIG. 13B, FIG. 13C and FIG. 13D are diagrammaticsectional views showing the method of forming the operatingsemiconductor layer in process order following to FIG. 12A, FIG. 12B,FIG. 12C and FIG. 12D;

[0040]FIG. 14 is a diagrammatic plan view showing a processed amorphoussilicon layer;

[0041]FIG. 15 is a diagrammatic plan view showing a state of theamorphous silicon layer on which a heat-retaining layer is formed;

[0042]FIG. 16 is a diagrammatic plan view showing a direction ofirradiation of a CW laser beam;

[0043]FIG. 17 is diagrammatic plan view showing a state of the crystalgrowth;

[0044]FIG. 18 is a photograph by an optical microscope showing acrystalline state of the completed operating semiconductor layer;

[0045]FIG. 19 is a TEM photograph showing the narrow region which is thesame region as that of the optical microscope photograph (theinclination angle φ:45°) in FIG. 18;

[0046]FIG. 20 is a diagrammatic sectional view showing a state ofpatterning to form a TFT operating semiconductor layer;

[0047]FIG. 21 is a diagrammatic plan view showing a state of a laserirradiation to the amorphous silicon layer in a modification example inthe second forming method;

[0048]FIG. 22A, FIG. 22B, FIG. 22C, and FIG. 22D are photographs by theoptical microscope showing crystalline states of the completed operatingsemiconductor layer;

[0049]FIG. 23A, FIG. 23B, and FIG. 23C are views showing result in amapping analysis observing by an EBSD system the same narrow region asthat of the photographs by the optical microscope in FIG. 22A, FIG. 22B,FIG. 22C, and FIG. 22D;

[0050]FIG. 24A, FIG. 24B and FIG. 24C are diagrammatic sectional viewsshowing a method of producing a TFT relating to the present embodimentin process order;

[0051]FIG. 25A, FIG. 25B and FIG. 25C are diagrammatic sectional viewsshowing the method of producing the TFT relating to the presentembodiment following to FIG. 24A, FIG. 24B and FIG. 24C in processorder;

[0052]FIG. 26A and FIG. 26B are diagrammatic sectional views showing themethod of producing the TFT relating to the present embodiment followingto FIG. 25A, FIG. 25B and FIG. 25C in process order;

[0053]FIG. 27A, FIG. 27B and FIG. 27C are diagrammatic sectional viewsshowing the method of producing the TFT relating to the presentembodiment following FIG. 26A and FIG. 26B in process order;

[0054]FIG. 28A and FIG. 28B are characteristic view respectively showingthe mobility of an n-type and a p-type TFT using the operatingsemiconductor layer according to the first forming method; and

[0055]FIG. 29A and FIG. 29B are characteristic view respectively showingthe mobility of an n-type and a p-type TFT using the operatingsemiconductor layer according to the second forming method.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] Hereinafter, concrete embodiments to which the present inventionis applied will be explained in detail with reference to the drawings.

[0057] In the present embodiment, a thin-film transistor (TFT) isexemplified as a semiconductor device, and the configuration thereofwill be explained as well as a method of production thereof.

[0058] -Structure of an Operating Semiconductor Layer-

[0059] On describing the method of production, structure of a TFToperating semiconductor layer which is a characteristic of the presentinvention will be explained first.

[0060] The most important point required to the operating semiconductorlayer characterizing the present invention is to make a channel portionof the operating semiconductor layer a single crystal structuresubstantially. It is important to realize the following mechanisms forforming the operating semiconductor layer having such a configuration ona substrate with no existing seed crystal.

[0061] (1) mechanism to form one crystal grain,

[0062] (2) mechanism to control the growth direction, and

[0063] (3) mechanism to restrain the occurrence of other crystal grainsduring the growth.

[0064] Concerning (1)

[0065] In order to form one crystal grain, it is necessary to removeexcess crystal grain boundary from a region where a single crystal isexpected to form.

[0066] Concerning (2)

[0067] Excimer Laser Crystallization (ELC) depends on a process ofmelting and solidification in high speed. The crystal grows from acrystal nucleus formed by chance on an interface between a siliconmolten and a foundation. It is extremely difficult to control theposition of the crystal nucleus. When the number of the crystal nucleiis small, the crystal grain diameter is far lager than the thickness ofa silicon layer, so that it can be considered that a lateral growthoccurs though the distance of the crystal grain is short. The size ofthe crystal is decided by the collision of the crystal grain which hasgrown from the adjacent crystal nucleus. The lateral growth is notcontrolled artificially, but a natural phenomenon. On the other hand, inthe crystallization process using energy beam, a CW laser here, tooutput energy continuously with respect to time, a flow pattern isformed by scanning the energy beam so that the growth direction can becontrolled over a certain distance.

[0068] Concerning (3)

[0069] In order to restrain the growth of the crystal grains other thanthe targeted one, it is required to control the temperature gradient ofthe semiconductor layer.

[0070] In order to form a channel region with single crystals, it isnecessary to prevent the crystal grain boundary which is to be theboundary of the flow pattern from entering into the channel region.Therefore, the present invention proposes a mechanism to prevent thecrystal grain boundary from entering into the channel region based onthe mechanisms (1) through (3), as will be described later.

[0071] -Forming Method of an Operating Semiconductor Layer-

[0072] A forming method of an operating semiconductor layer is describednext.

[0073] (First Forming Method)

[0074] Primarily, a first forming method is explained. FIG. 1A, FIG. 1B,FIG. 1C, FIG. 1D and FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D are diagrammaticsectional views showing the first forming method of the operatingsemiconductor layer in its process order.

[0075] First, as shown in FIG. 1A, a silicon oxide layer 2 which is tobe a buffer layer is formed on a glass substrate 1 in a layer thicknessof about 400 nm. Then as a semiconductor layer with a layer thickness ofabout 200 nm, here an amorphous silicon layer 3 made of amorphoussilicon is formed by a PECVD method. The layer thickness of theamorphous silicon layer 3 is made to be 400 nm or less, preferably about30 nm through about 200 nm, with respect to the relation with the layerthickness of the heat-retaining layer described later. Next, heatprocessing at 450° C. is applied on the glass substrate 1 for 2 hours toremove hydrogen.

[0076] Next, as shown in FIG. 1B, the amorphous silicon layer 3 isprocessed into an island shape. In the present embodiment, the amorphoussilicon layer 3 is patterned by photolithography and dry etching to beshaped so that it has a wide region 3 a and a narrow region 3 b and thenarrow region 3 b is connected to the wide region 3 a in a manner thatthe narrow region 3 b is positioned to be asymmetric with respect to thewide region 3 a as shown in FIG. 3. Here, the vicinity of the boundarybetween the wide region 3 a and the narrow region 3 b becomes a neckingregion.

[0077] Then, as shown in FIG. 1C, a silicon oxide layer 4 which servesas a separation layer is formed by the PECVD method to have the layerthickness of about 50 nm and to cover the whole surface (side face andupper face) of the amorphous silicon layer 3.

[0078] Next, as shown in FIG. 1D, an amorphous silicon layer is formedto have the layer thickness of about 250 nm by a plasma CVD method tocover the amorphous silicon layer 3 through the silicon oxide layer 4,and the amorphous silicon layer is changed into a polycrystallinesilicon layer 5 by a metal induce solid-phase growth using nickel (Ni).For a metal impurity to induce the solid-phase growth, any metal otherthan Ni can be used. At this time, the solid-phase growth temperature isset to be 570° C. and time for the heat processing is set to be 8 hours.Though the amorphous silicon layer having the layer thickness of about250 nm is changed into the polycrystalline silicon layer 5 through thisprocessing, the amorphous silicon layer 3 covered with the silicon oxidefilm 4 which serves as the separation layer is kept in a state ofamorphous silicon because the silicon oxide layer 4 prevents Ni fromdispersion.

[0079] The polycrystalline silicon layer 5 may be formed so as to coverthe amorphous silicon layer 3 by a chemical vapor growth method or aphysical evaporation method from the beginning. It is also preferable touse amorphous silicon.

[0080] Then, as shown in FIG. 2A and FIG. 4, the polycrystalline siliconlayer 5 is patterned in an island shape to cover the side portion of thenarrow region 3 b, and then the exposed silicon oxide layer 4 is removedusing HF solution. At this time, the surface of the narrow region 3 b isexposed except the side portion.

[0081] Then, as shown in FIG. 2B, the narrow region 3 b is irradiatedwith a CW laser beam, here a solid-state laser (DPSS laser) ofsemiconductor excitation (LD excitation), from the top surface in astate that the polycrystalline silicon layer 5 as a heat-retaining layerencloses the narrow region 3 b through the silicon oxide layer 4 fromthe side face to crystallize the amorphous silicone layer 3 so that theoperating semiconductor layer 11 is formed.

[0082] Here, as one example, the above-described solid-state laser issemiconductor LD excitation Nd: YVO₄ laser using second harmonic withwavelength of 532 nm, whose output is 10 W. In the solid-state laser ofthe semiconductor LD excitation, a noise (light noise) indicatinginstability of the energy beam is 0.1 rms % or less in a region of 10 Hzto 2 MHz, and an index of the energy beam output instability is lessthan ±1% per hour, which is extremely excellent compared to other energybeams.

[0083] Incidentally, a portion which the CW laser beam irradiates is notlimited to the front surface side of the substrate, but it may irradiatefrom the back face side.

[0084] As for the direction in irradiation (the scanning direction) ofthe CW laser beam, as shown in FIG. 5, the beam is scanned in parallelto the longitudinal direction of the narrow region 3 b, from the wideregion 3 a which is large in area toward the narrow region 3 b which issmall in area. At this time, the necking region where the width becomesnarrower abruptly produces so-called filtering effect, whereby manycrystal grain boundaries disappear in this region and the crystal grainboundary is restrained from entering into the narrow region 3 b.Therefore, a single crystal silicon is formed. Incidentally, whenirradiating the CW laser beam, it is also suitable to irradiate the CWlaser beam outputting energy continuously with its pulse modulated bymatching to the narrow region 3 b.

[0085] A mechanism to form a single crystal silicon by irradiation ofthe CW laser beam according to the forming method is described asfollows.

[0086] Since the amorphous silicon layer 3 is covered with a thickpolycrystalline silicon layer 5 which serves as a heat-retaining layeronly at side portions of the narrow region 3 b, the polycrystallinesilicon layer 5 at the side surface serves as a heat reservoir. As aresult, no crystal nucleus generates from the side edge of the narrowregion 3 b. In this case, crystallization proceeds by the progress ofthe temperature lowering from the center portion of the narrow region 3b. However, since only the side portion of the narrow region 3 b isselectively covered with the polycrystalline silicon layer 5, it is themost difficult to lower the temperature of this side portion andtherefore effective crystallization can be realized. The single crystalgrain selected in the necking region serves as a seed crystal at thetime of crystallization of the narrow region 3 b (FIG. 6A). Since the CWlaser beam is scanned in parallel to the narrow region 3 b, asolid-liquid interface also moves in parallel to the narrow region 3 b.Since crystallization progresses from only one seed crystal, a singlecrystal silicon is to be formed in the narrow region 3 b (FIG. 6B).

[0087] In the crystal growth in the wide region 3 a, a crystal nucleusis formed at the edge of the wide region 3 a, and the growth of thecrystal progresses toward the inside.

[0088] In the wide region 3 a, as shown in FIG. 7A, the crystal growthis performed in a flow pattern flowing in the scanning direction of alarge grain having 5 μm or more of a crystal grain diameter, namelycorresponding to 10 to 100 times as large as the grain diameter of thecrystal formed by excimer laser crystallization (ELC). At this time, thecrystal grain boundary progresses toward the center of the wide region 3a.

[0089] Actual result of observation with an optical microscope is shownin FIG. 7B. This image shows a view in which a crystal grain boundary isactualized through performing seccoetching.

[0090] An example of forming the narrow region 3 b to be symmetric withrespect to the wide region 3 a is shown in FIG. 7C to compare with thepresent example. Thus, since the crystal grain boundary of the flowpattern formed in the wide region 3 a has a tendency to progress towardthe center of the wide region 3 a, when the narrow region 3 b is set toplace in the central portion of the wide region 3 a, the crystal grainboundary enters into the narrow region 3 b in large quantity. At thistime, possibility of single crystal growth in the narrow region 3 bcomes to extremely low.

[0091] On the other hand, since the narrow region 3 b is formed to beasymmetric with respect to the wide region 3 a in this example, thecrystal grain boundary is to run obliquely towards the narrow region 3b. Accordingly, at the boundary portion in the narrow region 3 b to thewide region 3 a, the crystal grain boundary collides against the wall ofthe narrow region 3 b and disappears, so that entering to the inside ofthe narrow region 3 b is restrained. Therefore, the narrow region 3 b isquite easy to get a single crystal state.

[0092] Additionally, it is owing to the fact that the crystal grain hasa tendency to grow larger as the scanning distance is longer, becausethe CW laser beam is scanned from the wide region 3 a having a largearea toward the narrow region 3 b having a small area. Once a largecrystal grain is formed, the possibility of the crystal grain boundaryentering into the narrow region 3 b is decreased. Accordingly, it isdesirable that the width of the narrow region 3 b is narrower than thewidth of the crystal grain.

[0093] Furthermore, in the narrow region 3 b, at the time ofsolidification after melting by the CW laser beam, temperaturedistribution of low temperature at the central portion and hightemperature at the peripheral portion is formed. Owing to thistemperature distribution, since the temperature gradient from thecentral portion toward the peripheral portion is formed, even if acrystal grain boundary is mixed into the narrow region 3 b, it runs awaytoward the outside during growth of crystal. In other words, when thescanning distance becomes longer, all defect portions run outside sothat formation of the single crystal is promoted.

[0094] Due to the mechanism described above, the narrow region 3 b iscrystallized in a single crystal formation.

[0095] Then, as shown in FIG. 2C and FIG. 8, a portion where neither thesilicon oxide layer 4 nor the polycrystalline silicon layer 5 exists inthus formed operating semiconductor layer 11 is covered with a resistfilm 12.

[0096] As shown in FIG. 2D, after the polycrystalline silicon layer 5 isremoved by dry etching using the resist film 12 as a mask, the resistfilm 12 is removed by ashing treatment or the like, then the siliconoxide layer 4 is removed by HF solution.

[0097] As above, the operating semiconductor layer (silicon island) 11is completed.

[0098] An optical microscope photograph of a crystalline state of theoperating semiconductor layer 11 thus completed is shown in FIG. 10.

[0099] Here, seccoetching is executed to actualize the defect, and thecrystallinity of a narrow region 11 b is studied using a mask patternwhich remains only the narrow region 11 b. This is the reason why aportion of a wide region 11 a is disappeared. It is recognized from thephotograph that the narrow region 11 b is in a single crystal state.

[0100] By using thus formed silicon island, the TFT operatingsemiconductor layer 11 in a shape that the narrow region 11 b issymmetric with respect to the wide region 11 a may be formed by furthernew patterning as shown in FIG. 9. Here, since defects such as peelingoff of the layer are easy to occur at a peripheral edge portion of thesilicon island, a more excellent operating semiconductor layer having nodefects is formed by removal of the peripheral portion with thispatterning.

Modification Example

[0101] Considering an excellent crystal growth, a modification examplefor forming an operating semiconductor layer having a differentpatterning shape will be explained here.

[0102] In this example, on processing the amorphous silicon layer 3 intoan island shape, a cut-out 13 is formed at one end portion where aportion of the crystal grain boundary in the flow pattern of the wideregion 3 a comes near the narrow region 3 b during the later laser beamirradiation process, as shown in FIG. 11. Then, the crystal grainboundary in the flow pattern is further restrained from entering intothe narrow region 3 b, so that single crystallization is realized withmore reliability.

[0103] (Second Forming Method)

[0104] Next, a second forming method is explained. FIG. 12A, FIG. 12B,FIG. 12C, FIG. 12D and FIG. 13A, FIG. 13B, FIG. 13C, FIG. 13D arediagrammatic sectional views showing the second forming method of theoperating semiconductor layer in its process order.

[0105] First, as shown in FIG. 12A, a silicon oxide layer 2 which is tobe a buffer layer is formed on a glass substrate 1 in a layer thicknessof about 400 nm. Then as a semiconductor layer with layer thickness ofabout 200 nm, here an amorphous silicon layer 31 made of amorphoussilicon is formed by a PECVD method. The layer thickness of theamorphous silicon layer 31 is made to be 400 nm or less, preferablyabout 30 nm through about 200 nm, with respect to the relation with thelayer thickness of the heat-retaining layer. Next, heat processing at550° C. is applied on the glass substrate 1 for 2 hours to removehydrogen.

[0106] Next, as shown in FIG. 12B and FIG. 14, the amorphous siliconlayer 31 is patterned by photolithography and dry etching to be shapedso that it has a wide region 31 a and a narrow region 31 b and thenarrow region 31 b is connected to the wide region 31 a in a manner thatthe narrow region 31 b is positioned to be symmetric with respect to thewide region 31 a. Here, the vicinity of the boundary between the wideregion 31 a and the narrow region 31 b becomes a necking region.

[0107] Then, as shown in FIG. 12C, a silicon oxide layer 4 which servesas a separation layer is formed by the PECVD method to have the layerthickness of about 50 nm and to cover the whole surface (side face andupper face) of the amorphous silicon layer 31.

[0108] Next, as shown in FIG. 12D, an amorphous silicon layer is formedto have the layer thickness of about 250 nm by a plasma CVD method tocover the amorphous silicon layer 31 through the silicon oxide layer 4,and the amorphous silicon layer is changed into a polycrystallinesilicon layer 5 by a metal induce solid-phase growth using nickel (Ni).For a metal impurity to induce the solid-phase growth, any metal otherthan Ni can be used. At this time, the solid-phase growth temperature isset to be 570° C. and time for the heat processing is set to be 8 hours.Though the amorphous silicon layer having the layer thickness of about300 nm is changed into the polycrystalline silicon layer 5 through thisprocessing, the amorphous silicon layer 31 covered with the siliconoxide film 4 which serves as the separation layer is kept in a state ofamorphous silicon because the silicon oxide layer 4 prevents Ni fromdispersion.

[0109] The polycrystalline silicon layer 5 may be formed so as to coverthe amorphous silicon layer 31 by a chemical vapor growth method or aphysical evaporation method from the beginning. It is also preferable touse amorphous silicon.

[0110] Then, as shown in FIG. 13A and FIG. 15, the polycrystallinesilicon layer 5 is patterned in an island shape to cover the sideportion of the narrow region 31 b, and then the exposed silicon oxidelayer 4 is removed using HF solution. At this time, the surface of thenarrow region 31 b is exposed except the side portion.

[0111] Then, as shown in FIG. 13B, the narrow region 31 b is irradiatedwith a CW laser beam, here a solid-state laser (DPSS laser) ofsemiconductor excitation (LD excitation), from the top surface in astate that the polycrystalline silicon layer 5 as a heat-retaining layerencloses the narrow region 31 b through the silicon oxide layer 4 fromthe side face to crystallize the amorphous silicone layer 31 so that theoperating semiconductor layer 32 is formed.

[0112] As one example, the above-described solid-state laser, the CWlaser here, is semiconductor LD excitation Nd: YVO₄ laser using secondharmonic with wavelength of 532 nm, whose output is 10 W. In thesolid-state laser of a semiconductor LD excitation, a noise (lightnoise) indicating instability of the energy beam is 0.1 rms % or less ina region of 10 Hz to 2 MHz, and an index of the energy beam outputinstability is less than ±1% per hour, which is extremely excellentcompared to other energy beams.

[0113] Incidentally, a portion on which the CW laser beam irradiates isnot limited to the front surface side of the substrate, but it mayirradiate from the back surface side.

[0114] In this forming methods, on irradiating the CW laser beam to theamorphous silicon layer 31, as shown in FIG. 16, a scanning plane 42 ofa beam spot 41 of the CW laser beam is inclined by a predetermined angle(inclination angle φ) from a perpendicular position (indicated by Y axisin FIG. 16) to the longitudinal direction of the amorphous silicon layer31 (indicated by X axis in the FIG. 16), and the beam spot 41 is scannedin the perpendicular direction to the longitudinal direction of theamorphous silicon layer 31 (indicated by Y axis and arrow M in FIG. 16).Here, for the beam spot 41, it is preferable to use one which is in azonal shape or an elliptic shape and whose scanning plane 42 issubstantially a flat plane. At this time, since a portion where thewidth becomes narrower abruptly serves as a necking region, a singlecrystal silicon is formed.

[0115] A mechanism to form a single crystal silicon by irradiation ofthe CW laser beam according to the forming methods is described asfollows.

[0116] As shown in FIG. 17, in order to form the narrow region 31 b tobe a channel of the TFT into a single crystal, it is necessary torestrain the occurrence of the crystal nucleus on the narrow region 31 band to prevent the crystal grain boundary which is grown on a region Ahaving a large area in the wide region 31 a to become the boundary ofthe crystal grains from entering into the narrow region 31 b. In thisforming method, the beam spot 41 is scanned and irradiated by beinginclined toward the boundary portion of the narrow region 31 b to thewide region 31 a, and the crystal grain boundary is formed in aperpendicular direction to a boundary of the scanning plane 42 of thebeam spot 41. Therefore, the crystal grain boundary is formed obliquelyto the extent to which the beam spot 41 is inclined to the X axisdirection. Accordingly, even if the crystal grain boundary of onecrystal grain which grows from a crystal nucleus enters into the narrowregion 31 b, the crystal grain boundary runs obliquely toward the narrowregion 31 b, and at the boundary portion of the narrow region 31 b tothe wide region 31 a, the crystal grain boundaries collide against thewall of the narrow region 31 b and most of them disappear, whereby thecrystal grain boundaries are restrained from entering to the inside ofthe narrow region 31 b. Therefore, the narrow region 31 b is quite easyto get a single crystal state.

[0117] In this forming method, the crystal grain boundary entersobliquely with high reliability at the boundary portion between the wideregion 31 a and the narrow region 31 b, which is different from theabove-described first forming method. In other words, according to thisforming method, the collision of the crystal grain boundary against thewall of the narrow region 31 b is caused securely without depending on akind of contingency.

[0118] Considering the above description, it is preferable to make theinclination angle φ of the scanning plane 42 of the beam spot 41 be +15°through +75°, or −75° through −15°. This is because when the angle isequal to or less than +15° (equal to or more than −15°), it is difficultfor the crystal grain boundary to collide against the wall of the narrowregion 31 b, and when the angle is equal to or more than +75° (equal toor less than −75°), it is difficult to secure the effective irradiationof the CW laser beam to the amorphous silicon layer 31 since the rate ofthe single crystallization of the narrow region 31 b is lowered.

[0119] Since the amorphous silicon layer 31 is covered with a thickpolycrystalline silicon layer 5 which serves as a heat-retaining layeronly at side portions of the narrow region 31 b, the polycrystallinesilicon layer 5 at the side surface serves as a heat reservoir having alarge heat capacity. Therefore, cooling rate of the molten is made smalland the heat distribution of the amorphous silicon layer 31 iscontrolled, whereby the position of nucleus formation and direction ofcrystal growth are controlled. In this case, crystallization proceeds byprogress of the temperature lowering from the center portion of thenarrow region 31 b. However, since only the side portion of the narrowregion 31 b is selectively covered with the polycrystalline siliconlayer 5, it is the most difficult to lower the temperature of this sideportion and therefore effective crystallization can be realized. As aresult, the crystalline state having a large crystal grain diameter canbe realized with high reliability without occurrence of the crystaluncles from the sidewall of the narrow region 31 b.

[0120] Additionally, since there is a tendency that the crystal graingrows larger as the scanning distance of the laser is longer, it isbeneficial to grow the crystal in an oblique direction. Furthermore,similarly to the first forming method, by forming the narrow region 31 bat an asymmetric position with respect to the wide region 31 a and byforming the wide region 31 a large, it is possible to further extend thescanning distance of the laser. Once a large crystal grain is formed,the possibility of the crystal grain boundary entering into the narrowregion 31 b is decreased more.

[0121] In the narrow region 31 b, at the time of solidification aftermelting by the CW laser beam, temperature distribution of lowtemperature at the central portion and high temperature at theperipheral portion is formed. Owing to this temperature distribution,since the temperature gradient from the central portion toward theperipheral portion is formed, even if a crystal grain boundary is mixedinto the narrow region 31 b, it runs away toward the outside duringgrowth of the crystal. In other words, when the scanning distancebecomes longer, all defect portions run outside so that formation of thesingle crystal is promoted.

[0122] Due to the mechanism described above, the narrow region 31 b iscrystallized in a single crystal formation.

[0123] Thereafter, similarly to the first forming method, as shown inFIG. 13C, a portion where neither the silicon oxide layer 4 nor thepolycrystalline silicon layer 5 exists in thus formed operatingsemiconductor layer 32 is covered with a resist film 12.

[0124] As shown in FIG. 13D, after the polycrystalline silicon layer 5is removed by dry etching using the resist film 12 as a mask, the resistfilm 12 is removed by ashing treatment or the like, then the siliconoxide layer 4 is removed by HF solution.

[0125] As above, the operating semiconductor layer (silicon island) 32is completed.

[0126] A photograph by an optical microscope of a crystalline state ofthe operating semiconductor layer 32 thus completed is shown in FIG. 18.

[0127] Here, as an example when crystallizing by giving the beam spot aninclination angle φ, one where the inclination angle φ is equal to 45°is exemplified. It is recognized that a single crystal grain is formedwithout a large crystal grain boundary in the narrow region.Additionally, since there is not recognized a great change in color ofthe interference colors of the layer in the narrow region, it is knownthat a flat layer can be obtained. As for the flatness of the operatingsemiconductor layer, it is considered to be sufficiently flat whenroughness of the surface Ra is about 7 or less. Actually, when studyingthe roughness of the surface Ra in the narrow region by an observationimage of AFM, Ra is equal to 4 nm.

[0128] Next, a result in an observation by TEM of the narrow region thatis the same region as the optical microscope photograph in FIG. 18 (theinclination angle φ: 45°) is shown in FIG. 19.

[0129] Clear pattern without dislocation and the like is seen in anelectron diffraction pattern and no crystal grain boundary is seen inthe narrow region of about 8 μm×20 μm, so that a single crystal grain isrecognized. Furthermore, it is recognized from the electron diffractionpattern that the single crystalline state in the narrow region has (110)orientation. Similarly, it is possible to be controlled to have (100)orientation as the single crystalline state. Actually, when the inventorstudies the single crystalline state in the narrow region, it isrecognized that it is easy for the crystal to have (100) orientation ifthe inclination angle φ is 150 to 45°, preferably 30° to 45°, and tohave (110) orientation if the inclination angle φ is 45° to 75°,preferably 45° to 60°.

[0130] As above, according to the present forming method, it is possibleto form a single crystal grain having excellent crystallinity and tocontrol the orientation of the crystal when crystallizing the narrowregion 31 b of the amorphous silicon layer 31.

[0131] By using thus formed silicon island the TFT operatingsemiconductor layer 32 having a wide region 32 a and a narrow region 32b may be formed by further new patterning as shown in FIG. 20. Here,since defects such as peeling off of the layer are easy to occur at aperipheral edge portion of the silicon island, the excellent operatingsemiconductor layer without defects is formed by removal of theperipheral edge portion by this patterning.

Modification Example

[0132] In the aforementioned second forming method, on irradiating theCW laser beam to the amorphous silicon layer 31, it is disclosed thatthe beam spot 41 is scanned in the perpendicular direction to thelongitudinal direction of the amorphous silicon layer 31 by incliningthe scanning plane 42 of the beam spot 41 by the inclination angle φ. inthis modification example, however, as shown in FIG. 21, the scanningplane 42 of the beam spot 41 is inclined by the inclination angle φ andthe beam spot 41 is scanned along a direction of the inclination angle φ(indicated by arrow N in FIG. 21). Incidentally, in this modificationexample, only the scanning direction of the beam spot 41 is differentfrom that of the second forming method, but the shape of the operatingsemiconductor layer 32, the aspect and mechanism of crystallization, thestructure and usage (except the scanning direction) of the CW laser, andthe like are the same as those of the second forming method.

[0133] A photograph by an optical microscope of a crystalline state ofthe completed operating semiconductor layer 32 is shown in FIG. 22.

[0134] Here, as respective examples when crystallizing by giving thebeam spot an inclination angle φ, those with the inclination angle φ andthe scanning direction of −45°, 30°, 45°, and 60° are exemplifiedrespectively in FIG. 22A, FIG. 22B, FIG. 22C, and FIG. 22D. In therespective photographs, it is recognized that a single crystal grain isformed without a large crystal grain boundary in the narrow region.Additionally, since a great change in color of the interference colorsof the layer is not seen in the narrow region, it is recognized that aflat layer can be obtained.

[0135] Next, a result in a mapping analysis is shown in FIG. 23A, FIG.23B and FIG. 23C where the same narrow regions as the photographs by theoptical microscope in FIG. 22A, FIG. 22B, FIG. 22C, and FIG. 22D (theinclination angle φ and the scanning direction of 30°, 45°, and 60°) areobserved by an EBSD (Electron Back Scattered Diffraction) system. FIG.23A, FIG. 23B and FIG. 23C correspond to the inclination angle φ and thescanning direction of 30°, 45° and 60° respectively. In each of FIG.23A, FIG. 23B and FIG. 23C, which direction the orientation of thecrystal grain surface points to with respect to (100) is indicated bycolor of the basic triangle.

[0136] Since there is no great change in color and it is indicated bythe same color in the whole narrow region in an IPF (Inverse PoleFigure) mapping analysis which shows an indicator of the crystalorientation, it is recognized that a single crystal grain is formed.Furthermore, since the crystal grain in the narrow region can be clearlyseen in an IQ (Image Quality) mapping analysis which shows an indicatorof clearness in the EBSD system, it is recognized that the crystal grainhaving a quite excellent crystallinity where neither a crystal grainboundary nor a surface strain exists is formed in the narrow region.

[0137] Additionally, when any portions of the narrow region formed bythe laser scanning at the same inclination angle φ and the same scanningdirection are respectively selected and analyzed by the EBSD, theorientations of the respective crystals are relatively close to (100) atthe same inclination angle φ and the scanning direction. This indicatesthat it is possible to control the orientation of the crystal in certainextent by adjusting the inclination angle φ and the scanning direction.Concretely, when the inventor studies the single crystalline state inthe narrow region, it is recognized that it is easy for the crystal tohave (100) orientation if the inclination angle φ is 15° to 45°,preferably 30° to 45°, and to have (110) orientation if the inclinationangle φ is 45° to 75°, preferably 45° to 60°.

[0138] In this modification, similarly to the second forming method,collision of the crystal grain boundary against the wall of the narrowregion 31 b can be caused securely without depending on a kind ofcontingency, whereby it is possible to make the narrow region 31 bbecome a single crystalline state of a large grain diameter with highreliability.

[0139] -Production of TFT-

[0140] Using an operating semiconductor layer 11 or 32 formed as above,a TFT (n-channel TFT) is produced. FIG. 24A to FIG. 27C are diagrammaticsectional views showing a production method of the TFT relating to thepresent embodiment in the process order. Description is made belowassuming that the operating semiconductor layer 11 is used according tothe first forming method.

[0141] First, as shown in FIG. 24A, the operating semiconductor layer 11which is formed by the above method is prepared above a glass substrate21 through a silicon oxide layer 22 which serves as a buffer. Here, anarrow region 11 b of the operating semiconductor layer 11 serves as achannel.

[0142] Then, as shown in FIG. 24B, a silicon oxide layer 23 which is tobe a gate oxide film having the layer thickness of about 120 nm isformed on the operating semiconductor layer 11 by a PECVD method. Atthis time, other methods, for instance, an LPCVD method or a sputteringmethod may be used.

[0143] Then, as shown in FIG. 24C, an aluminum film (or an aluminumalloy film) 24 is formed to have the film thickness of about 350 nm by asputtering method.

[0144] Next, as shown in FIG. 25A, the aluminum film 24 is patternedinto a shape of an electrode by photolithography and following dryetching to form a gate electrode 24.

[0145] Then, as shown in FIG. 25B, the silicon oxide layer 23 ispatterned using the patterned gate electrode 24 as a mask to form thegate oxide film 23 copying the shape of the gate electrode 24.

[0146] Then, as shown in FIG. 25C, the gate electrode 24 of theoperating semiconductor layer 11 is ion doped on its both side portionsusing the gate electrode 24 as a mask. Concretely, an n-type impurity,phosphorus (P) here, is ion doped under the condition of accelerationenergy 10 keV and dose amount 5×10¹⁵/cm², to form a source/drain region.

[0147] Then, as shown in FIG. 26A, after the excimer laser irradiationis applied on the source/drain region to activate the phosphorustherein, as shown in FIG. 26B, SiN is deposited with the layer thicknessof about 300 nm to cover the whole surfaces so as to form an interlayerinsulation layer 25.

[0148] Then, as shown in FIG. 27A, each contact hole 26 which allows asurface portion of the gate electrode 24 and a surface portion of thesource/drain region of the operating semiconductor layer 11 to exposerespectively is formed as an aperture on the interlayer insulation layer25.

[0149] Then, as shown in FIG. 27B, after a metal film 27 made ofaluminum or the like is formed so as to embed each contact hole 26, themetal film 27 is patterned to form a wiring 27 which conducts to thegate electrode 24 and the source/drain region of the operatingsemiconductor layer 11 through the contact holes 26 respectively asshown in FIG. 27C.

[0150] After that, the n-type TFT is completed after formation and thelike of a heat-retaining layer covering the whole surface.

[0151] Actually, the n-type TFT of this embodiment is produced in such amanner that the operating semiconductor layer 11 is in the channellength of about 5 μm and in the channel width of about 3 μm. As a resultof measuring the mobility thereof, the high mobility so much as 560cm²/Vs can be attained (FIG. 28A). Incidentally, as a result ofmeasuring the mobility of a p-type TFT which is produced using the samemethod, the mobility of 200 cm²/Vs can be realized (FIG. 28B).

[0152] Additionally, using the operating semiconductor layer 32according to the second forming method, the n-type TFT (the channellength of about 5 μm, the channel width of about 3 μm) is produced inthe same manner as FIG. 24A to FIG. 27C. As a result of measuring themobility thereof, the high mobility so much as 580 cm²/Vs can berealized (FIG. 29A). Incidentally, as a result of measuring the mobilityof a p-type TFT which is produced using the same method, the mobility of234 cm²/Vs can be realized (FIG. 29B).

[0153] As described above, according to the present embodiment, anexcellent operating semiconductor layer 11 or 32 having a negligiblysmall effect of the crystal grain boundary can be formed to realize aTFT with extremely high mobility.

[0154] It should be noted that though amorphous silicon is used as asemiconductor layer in the present embodiment, polycrystalline siliconother than the amorphous silicon can be used. In addition, thispolycrystalline silicon can be formed by a metal induce solid-phasegrowth. It is also preferable to improve quality of crystal by raisingtemperature of the substrate or to relax the heat strain oncrystallizing. Furthermore, a mixture (compound) of silicon andgermanium can be used.

[0155] The semiconductor device explained in the present embodiment canbe applied to a liquid crystal display (LCD) of a peripheral circuitintegrated type provided with TFT, a system-on-panel, a system-on-glassand further an SOI element.

[0156] According to the present invention, it is possible to provide athin-film type semiconductor device which realizes extremely highmobility by forming an operating semiconductor layer from a thinsemiconductor layer having a negligibly small effect of the crystalgrain boundary, and to provide a method of production of thesemiconductor device enabling to produce the semiconductor device easilyand securely.

[0157] The present embodiments are to be considered in all respects asillustrative and no restrictive, and all changes which come within themeaning and range of equivalency of the claims are therefore intended tobe embraced therein. The invention may be embodied in other specificforms without departing from the spirit or essential characteristicsthereof.

What is claimed is:
 1. A semiconductor device, comprising: a substrate; and an operating semiconductor layer pattern-formed above said substrate, wherein said operating semiconductor layer is shaped so that a wide region and a narrow region are connected to each other; wherein the wide region is in a flow pattern state having a large crystal grain and a direction of a crystal grain boundary of the flow pattern is not parallel to a longitudinal direction of the narrow region; and wherein the narrow region is substantially in a single crystalline state.
 2. The semiconductor device according to claim 1, wherein the narrow region functions as a channel.
 3. The semiconductor device according to claim 1, wherein the narrow region is provided with a cut-out formed on one end portion near a portion of the crystal grain boundary of the flow pattern.
 4. The semiconductor device according to claim 1, wherein the width of the narrow region is narrower than the width of the crystal grain.
 5. A method of production of a thin film type semiconductor device provided with a substrate and an operating semiconductor layer pattern-formed above the substrate, comprising the steps of: forming a semiconductor layer to be the operating semiconductor layer above the substrate; processing the semiconductor layer to be shaped so that it has a wide region and a narrow region and that the narrow region is connected to the wide region in a manner that the narrow region is positioned to be asymmetric with respect to the wide region; forming a heat-retaining layer of the narrow region to cover a side portion of the narrow region selectively through a separation layer after processing the semiconductor layer; and crystallizing the semiconductor layer by irradiating energy beam to the semiconductor layer along a longitudinal direction of the narrow region from the wide region toward the narrow region in a state that the heat-retaining layer is formed.
 6. The method of production of the semiconductor device according to claim 5, wherein a cut-out is formed in the narrow region on processing the semiconductor layer.
 7. The method of production of the semiconductor device according to claim 5, wherein after crystallization of the semiconductor layer, the operating semiconductor layer is patterned by removing a peripheral edge portion of the semiconductor layer in order to make the semiconductor layer be shaped so that the narrow region is positioned to be symmetric with respect to the wide region.
 8. The method of production of the semiconductor device according to claim 5, wherein the energy beam outputs energy continuously with respect to time.
 9. The method of production of the semiconductor device according to claim 8, wherein the energy beam outputting energy continuously with respect to time is a CW laser beam.
 10. The method of production of the semiconductor device according to claim 9, wherein the CW laser beam is a solid-state laser beam of semiconductor excitation.
 11. The method of production of the semiconductor device according to claim 8, wherein the output instability of the energy beam is less than ±1% per hour.
 12. The method of production of the semiconductor device according to claim 5, wherein the semiconductor layer is formed to have the thickness of 400 nm or less.
 13. The method of production of the semiconductor device according to claim 5, wherein the narrow region is formed to be a channel for the operating semiconductor layer.
 14. The method of production of the semiconductor device according to claim 5, wherein the narrow region is formed to have the width thereof narrower than the width of the crystal grain.
 15. The method of production of the semiconductor device according to claim 5, wherein a beam spot of the energy beam is in a zonal shape or an elliptic shape and a scanning plane thereof is substantially a flat plane.
 16. The method of production of the semiconductor device according to claim 5, wherein the CW laser beam outputting energy continuously is irradiated with its pulse modulated by matching to the narrow region (the position to be a channel).
 17. A method of production of a thin-film type semiconductor device provided with a substrate and an operating semiconductor layer pattern-formed above the substrate, comprising the steps of: forming a semiconductor layer to be the operating semiconductor layer above the substrate; processing the semiconductor layer to be shaped so that it has a wide region and a narrow region; and crystallizing the semiconductor layer by irradiating energy beam to the semiconductor layer in such a manner that a scanning plane of a beam spot of the energy beam is inclined from a perpendicular position to a longitudinal direction of the semiconductor layer.
 18. The method of production of the semiconductor device according to claim 17, wherein the beam spot is scanned along the longitudinal direction of the semiconductor layer when irradiating the energy beam to the semiconductor layer.
 19. The method of production of the semiconductor device according to claim 17, wherein the beam spot is scanned in a perpendicular direction to the scanning plane of the inclined beam spot when irradiating the energy beam to the semiconductor layer.
 20. The method of production of the semiconductor device according to claim 17, wherein the inclination angle of the scanning plane of the beam spot is between +15° and +75°, or between −75° and −15°.
 21. The method of production of the semiconductor device according to claim 17, wherein a cut-out is formed in the narrow region when processing the semiconductor layer.
 22. The method of production of the semiconductor device according to claim 18, further comprising the step of: forming a heat-retaining layer of the narrow region to cover a side portion of the narrow region through a separation layer after processing the semiconductor layer, wherein the energy beam is irradiated to the semiconductor layer along the longitudinal direction of the narrow region in a state that the heat-retaining layer is formed.
 23. The method of production of the semiconductor device according to claim 17, wherein after crystallization of the semiconductor layer, the operating semiconductor layer is patterned by removing a peripheral edge portion of the semiconductor layer in order to make the semiconductor layer be shaped so that the narrow region is positioned to be symmetric with respect to the wide region.
 24. The method of production of the semiconductor device according to claim 17, wherein the energy beam outputs energy continuously with respect to time.
 25. The method of production of the semiconductor device according to claim 24, wherein the energy beam outputting energy continuously with respect to time is a CW laser beam.
 26. The method of production of the semiconductor device according to claim 25, wherein the CW laser beam is a solid-state laser beam of semiconductor excitation.
 27. The method of production of the semiconductor device according to claim 24, wherein the output instability of the energy beam is less than ±1% per hour.
 28. The method of production of the semiconductor device according to claim 17, wherein the semiconductor layer is formed to have the thickness of 400 nm or less.
 29. The method of production of the semiconductor device according to claim 17, wherein the narrow region is formed to be a channel for the operating semiconductor layer.
 30. The method of production of the semiconductor device according to claim 17, wherein the narrow region is formed to have the width thereof narrower than the width of the crystal grain.
 31. The method of production of the semiconductor device according to claim 17, wherein the beam spot of the energy beam is in a zonal shape or an elliptic shape and the scanning plane thereof is substantially a flat plane.
 32. The method of production of the semiconductor device according to claim 17, wherein the CW laser beam outputting energy continuously is irradiated with its pulse modulated by matching to the narrow region (the position to be a channel). 